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d a t a sh eet product speci?cation supersedes data of 1995 jul 13 file under integrated circuits, ic20 1997 mar 14 integrated circuits p83cl781; p83cl782 low voltage 8-bit microcontrollers with uart and i 2 c-bus
1997 mar 14 2 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 contents 1 features 2 general description 3 applications 4 ordering information 5 block diagram 6 functional diagram 7 pinning information 7.1 pinning 7.2 pin description 8 functional description overview 8.1 general 8.2 cpu timing 9 memory organization 9.1 program memory 9.2 data memory 9.3 special function registers 9.4 addressing 10 i/o facilities 10.1 ports 10.2 port options 10.3 port 0 options 10.4 set/reset options 11 timer/event counters 11.1 timer 0 and timer 1 11.2 timer t2 11.3 timer/counter 2 control register (t2con) 12 reduced power modes 12.1 idle mode 12.2 power-down mode 12.3 wake-up from power-down mode 12.4 status of external pins 12.5 power control register (pcon) 13 i 2 c-bus serial i/o 13.1 serial control register (s1con) 13.2 serial status register (s1sta) 13.3 data shift register (s1dat) 13.4 address register (s1adr) 14 standard serial interface sio0: uart 14.1 multiprocessor communications 14.2 serial port control and status register (s0con) 14.3 baud rates 15 interrupt system 15.1 external interrupts int2 to int9 15.2 interrupt priority 15.3 interrupt registers 16 oscillator circuitry 17 reset 17.1 external reset using the rst pin 17.2 power-on reset 18 special function registers overview 19 instruction set 20 limiting values 21 dc characteristics 22 ac characteristics 22.1 program memory 22.2 external data memory 23 package outlines 24 soldering 24.1 introduction 24.2 dip 24.3 qfp 25 definitions 26 life support applications 27 purchase of philips i 2 c components
1997 mar 14 3 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 1 features full static 80c51 cpu 8-bit cpu, rom, ram, i/o in a 40-lead dip or 44-lead qfp package 16 kbytes rom, expandable externally to 64 kbytes 256 bytes ram, expandable externally to 64 kbytes four 8-bit ports, 32 i/o lines three 16-bit timer/event counters external memory expandable up to 128 kbytes: ram up to 64 kbytes and rom up to 64 kbytes on-chip oscillator suitable for rc, lc, quartz crystal or ceramic resonator fifteen source, fifteen vector interrupt structure with two priority levels full duplex serial port (uart) i 2 c-bus interface for serial transfer on two lines enhanced architecture with: C non-page oriented instructions C direct addressing C four 8 byte ram register banks C stack depth limited only by available internal ram (maximum 256 bytes) C multiply, divide, subtract and compare instructions reduced power consumption through power-down and idle modes wake-up via external interrupts at port 1 single supply voltage of 1.8 to 6.0 v operating ambient temperature: C 83cl781: - 40 to +85 c C 83cl782: - 25 to +55 c. frequency range of dc to 12 mhz very low current consumption. 2 general description the term p83cl78x is used throughout this data sheet to refer to both the p83cl781 and p83cl782; differences between the devices are highlighted in the text. the p83cl78x is manufactured in an advanced cmos technology. the p83cl78x has the same instruction set as the 80c51, consisting of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. the device has low power consumption and a wide range of supply voltage; there are two software-selectable modes of reduced activity for further power reduction: idle and power-down. for emulation purposes, the p85cl781 (piggy-back version) with 256 bytes of ram is recommended. the p83cl782 is a faster version of the p83cl781 and operates at a maximum frequency of 12 mhz at v dd 3 3.1 v. this data sheet details the specific properties of the p83cl78x. for details of the 80c51 core and the i 2 c-bus see data handbook ic20 . 3 applications the p83cl78x is an 8-bit general purpose microcontroller especially suited for cordless telephone applications. the p83cl78x also functions as an arithmetic processor having facilities for both binary and bcd arithmetic plus bit-handling capabilities.
1997 mar 14 4 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 4 ordering information note 1. refer to the order entry form (oef) for this device for the full type number, including options/program. type number (1) package name description version p83cl781hfp dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 p83cl782hdp p83cl781hfh qfp44 plastic quad ?at package; 44 leads (lead length 2.35 mm); body 14 14 2.2 mm sot205-1 P83CL782HDH p83cl781hfh qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 p83cl781hdh
1997 mar 14 5 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 5 block diagram fig.1 block diagram. handbook, full pagewidth mla601 3 3 1 2 0 3 3 rd wr psen xtal2 xtal1 ad0 to 7 a8 to 15 ea 3 3 3 3 sda scl dd v rxd txd p3 p2 p1 p0 t0 t1 int0 int1 0 1 alternative function of port 0 alternative functions of port 1 2 3 alternative function of port 2 alternative function of port 3 parallel i/o ports and external bus serial uart port 16-bit timer/ event counter two 16-bit timer/ event counters (t0, t1) 80c51 core excluding rom/ram cpu program memory data memory 8-bit internal bus 16 kbyte rom 256 byte ram ss v ale i 2 c interface p83cl781 p83cl782 rst 1 t2ex t2 1 1
1997 mar 14 6 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 6 functional diagram handbook, full pagewidth mbh885 port 0 ss v dd v port 1 port 3 low order address and data bus (ad0 to ad7) port 2 high order address bus (a8 to a15) t2 int2 t2ex int3 int4 int5 int6 scl sda rst xtal1 xtal2 rxd/data txd/clock t0 t1 rd wr int1 int0 p83cl781 p83cl782 psen ea ale int8 int9 int7 fig.2 functional diagram.
1997 mar 14 7 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 7 pinning information 7.1 pinning fig.3 pin configuration for dip40 package. mla603 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 21 22 23 24 25 26 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 p2.7/a15 p2.6/a14 p2.5/a13 ea psen p1.5/int7 rst p1.6/int8/scl p1.7/int9/sda p3.4/t0 p3.5/t1 p3.0/rxd/data p3.1/txd/clock p3.2/int0 p3.3/int1 ale p83cl781 p83cl782 xtal2 xtal1 p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 v ss p3.7/rd p3.6/wr v dd p1.4/int6 p1.3/int5 p1.2/int4 p1.1/int3/t2ex p1.0/int2/t2 p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3
1997 mar 14 8 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 handbook, full pagewidth p83cl781 p83cl782 p1.5/int7 p1.6/int8/scl p1.7/int9/sda rst p3.0/rxd/data n.c. p3.1/txd/clock p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 v ss ss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 test/v p2.5/a13 p2.6/a14 p2.7/a15 psen ale n.c. ea p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 v dd n.c. p1.0/int2/t2 p1.1/int3/t2ex p1.2/int4 p1.3/int5 p1.4/int6 mla604 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 fig.4 pin configuration for qfp44 packages.
1997 mar 14 9 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 7.2 pin description symbol pin description dip40 qfp44 p1.0/int2/t2 1 40 port 1: 8-bit bidirectional i/o port (p1.0 to p1.7). port pins that have logic 1s written to them are pulled high by internal pull-ups, and in this state can be used as inputs (note that p1.6 and p1.7 are open-drain only). as inputs, port 1 pins that are externally pulled low will source current (i il ) due to the internal pull-ups. port 1 output buffers can sink/source 4 ls ttl loads. alternative functions: C int2 to int9 are external interrupt inputs C t2 and t2ex are the timer/event counter 2 inputs C scl and sda are the i 2 c-bus clock and data lines. p1.1/int3/t2ex 2 41 p1.2/int4 3 42 p1.3/int5 4 43 p1.4/int6 5 44 p1.5/int7 6 1 p1.6/int8/scl 7 2 p1.7/int9/sda 8 3 rst 9 4 reset: a high level on this pin for two machine cycles while the oscillator is running, resets the device. n.c. - 6 not connected. p3.0/rxd/data 10 5 port 3: 8-bit bidirectional i/o port (p3.0 to p3.7). same characteristics as port 1. alternative functions: C rxd/data is the uart serial data input (asynchronous) or data i/o (synchronous) C txd/clock is the uart serial data output (asynchronous) or clock output (synchronous) C int0 and int1 are external interrupt lines C t0 and t1 are external inputs for timer 0 and timer 1 respectively C wr is the external memory write strobe and rd is the external memory read strobe. p3.1/txd/clock 11 7 p3.2/ int0 12 8 p3.3/ int1 13 9 p3.4/t0 14 10 p3.5/t1 15 11 p3.6/ wr 16 12 p3.7/ rd 17 13 xtal2 18 14 crystal output: output of the inverting ampli?er that forms the oscillator. left open-circuit when an external oscillator clock is used. xtal1 19 15 crystal input: input to the inverting ampli?er that forms the oscillator, also the input for an externally generated clock source. v ss 20 16 ground: circuit ground potential. test/v ss - 17 test input: must be connected to v ss or left open. p2.0/a8 21 18 port 2: 8-bit bidirectional i/o port (p2.0 to p2.7). same characteristics as port 1. high-order addressing: a8 to a15 make up the high-order address byte during accesses to external memory that use 16-bit addresses (movx@dptr). in this application the pins use the strong internal pull-ups when emitting logic 1's. during accesses to external memory that use 8-bit addresses (movx@ri), the pins emit the contents of the p2 special function register. p2.1/a9 22 19 p2.2/a10 23 20 p2.3/a11 24 21 p2.4/a12 25 22 p2.5/a13 26 23 p2.6/a14 27 24 p2.7/a15 28 25
1997 mar 14 10 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 psen 29 26 program store enable: read strobe to external program memory. when executing code out of external program memory, psen is activated twice each machine cycle. however, during each access to external data memory two psen activations are skipped. ale 30 27 address latch enable: latches the low byte of the address during accesses to external memory. it is activated every six oscillator periods and may be used for external timing or clocking purposes. n.c. - 28 not connected. ea 31 29 external access: when ea is held high, the cpu executes out of the internal program memory (unless the program counter exceeds 3fffh). when ea is held low, the cpu executes out of external program memory regardless of the value of the program counter. p0.7/ad7 32 30 port 0: 8-bit open-drain bidirectional i/o port (p0.7 to p0.0). as an open-drain output port it can sink/source 8 ls ttl loads. port 0 pins that have logic 1s written to them ?oat, and in this state will function as high-impedance inputs. low-order addressing: ad7 to ad0 provide the multiplexed low-order address and data bus during accesses to external memory. in this application the pins use the strong internal pull-ups when emitting logic 1s. p0.6/ad6 33 31 p0.5/ad5 34 32 p0.4/ad4 35 33 p0.3/ad3 36 34 p0.2/ad2 37 35 p0.1/ad1 38 36 p0.0/ad0 39 37 v dd 40 38 power supply . n.c. - 39 not connected. symbol pin description dip40 qfp44
1997 mar 14 11 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 8 functional description overview this chapter gives a brief overview of the device. the detailed functional description is in the following chapters: chapter 9 memory organization chapter 10 i/o facilities chapter 11 timer/event counters chapter 12 reduced power modes chapter 13 i 2 c-bus serial i/o chapter 14 standard serial interface sio0: uart chapter 15 interrupt system chapter 16 oscillator circuitry chapter 17 reset. 8.1 general the p83cl78x is a stand-alone high-performance cmos microcontroller designed for use in real-time applications such as instrumentation, industrial control, intelligent computer peripherals and consumer products. the device provides hardware features, architectural enhancements and new instructions to function as a controller for applications requiring up to 64 kbytes of program memory and/or up to 64 kbytes of data storage. the p83cl78x contains a non-volatile 16 kbyte read-only program memory; a static 256 byte read/write data memory; 32 i/o lines; three 16-bit timer/event counters; a fifteen-source, two priority-level, nested interrupt structure and on-chip oscillator and timing circuit. the device has two software-selectable modes of reduced activity for power reduction: idle mode ; freezes the cpu while allowing the timers, serial i/o and interrupt system to continue functioning. power-down mode ; saves the ram contents but freezes the oscillator causing all other chip functions to be inoperative. in addition, two serial interfaces are provided on-chip: a standard uart serial interface, and a standard i 2 c-bus serial interface. the i 2 c-bus serial interface has byte-oriented master and slave functions allowing communication with the whole family of i 2 c-bus compatible devices. 8.2 cpu timing a machine cycle consists of a sequence of 6 states. each state lasts for two oscillator periods, thus a machine cycle takes 12 oscillator periods or 1 m s if the oscillator frequency (f osc ) is 12 mhz.
1997 mar 14 12 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 9 memory organization the p83cl78x has a 16 kbyte program memory (rom) plus 256 bytes of data memory (ram) on-chip. the device has separate address spaces for program and data memory (see fig.6). using ports p0 and p2, the p83cl78x can address up to 128 kbytes of external memory. the cpu generates both read ( rd) and write ( wr) signals for external data memory accesses, and the read strobe ( psen) for external program memory. 9.1 program memory the p83cl78x contains 16 kbytes of internal rom. after reset the cpu begins execution at location 0000h. the lower 16 kbytes of program memory can be implemented in either on-chip rom or external memory. if the ea pin is strapped to v dd , then program memory fetches from addresses 0000h through to 3fffh are directed to the internal rom. fetches from addresses 4000h through to ffffh are directed to external rom. program counter values greater than 3fffh are automatically addressed to external memory regardless of the state of the ea pin. 9.2 data memory the p83cl78x contains 256 bytes of internal ram and 34 special function registers (sfrs). the memory map (fig.6 ) shows the internal data memory space divided into the lower 128 bytes, the upper 128 bytes and the sfr space. internal ram locations 0 to 127 are directly and indirectly addressable. internal ram locations 128 to 255 are only indirectly addressable. the special function register locations 128 to 255 bytes are only directly addressable. 9.3 special function registers the upper 128 bytes are the address locations of the special function registers. figures 7 and 8 show the special function registers space. the sfrs include the port latches, timers, peripheral control, serial i/o registers, and so on. these registers can only be accessed by direct addressing. there are 128 addressable locations in the sfr address space (sfrs with addresses divisible by eight). 9.4 addressing the p83cl78x has five methods for addressing source operands: register direct register-indirect immediate base-register plus index-register-indirect. the first three methods can be used for addressing destination operands. most instructions have a destination/source field that specifies the data type, addressing methods and operands involved. for operations other than movs, the destination operand is also a source operand. fig.5 the lower 128 bytes of internal ram. a lfpage mla560 - 1 r7 r0 07h 0 r7 r0 0fh 08h r7 r0 17h 10h r7 r0 1fh 18h 2fh 7fh 20h 30h bit-addressable space (bit addresses 0 to 7f) 4 banks of 8 registers (r0 to r7)
1997 mar 14 13 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 access to memory addressing is as follows: registers in one of the four register banks through register, direct or register-indirect 256 bytes of internal data ram through direct or register-indirect special function registers through direct external data memory through register-indirect program memory look-up tables through base-register plus index-register-indirect. the p83cl78x is classified as an 8-bit device since the internal rom, ram, special function registers, arithmetic logic unit and external data bus are all 8-bits wide. it performs operations on bit, nibble, byte and double-byte data types. facilities are available for byte transfer, logic and integer arithmetic operations. data transfer, logic and conditional branch operations can be performed directly on boolean variables to provide excellent bit handling. fig.6 memory map. handbook, full pagewidth mla605 internal data ram 255 127 0 external (ea = 0) internal (ea = 1) internal data memory external data memory program memory external 64 kbytes 64 kbytes 16 kbytes 16 kbytes overlapped space 0 16 kbytes special function registers (indirect only)
1997 mar 14 14 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.7 special function register memory map (continued in fig.8). mla606 - 1 fe ff fd fc fb fa f9 f8 f6 f7 f5 f4 f3 f2 f1 f0 ee ef ed ec eb ea e9 e8 e6 e7 e5 e4 e3 e2 e1 e0 de df dd dc db da d9 d8 d6 d7 d5 d4 d3 d2 d1 d0 ce cf cd cc cb ca c9 c8 c6 c7 c5 c4 c3 c2 c1 c0 bit address register mnemonic ffh direct byte address (hex) feh fdh fch f8h f0h efh eeh edh ech ebh eah e8h e0h dbh dah d9h d8h d0h cfh ceh cdh cch cbh cah c9h c8h c0h sfrs containing directly addressable bits ip1 b ien1 acc s1adr s1dat s1sta s1con psw th2 tl2 rcap2h rcap2l t2con irq1 ix1 e9h
1997 mar 14 15 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.8 special function register memory map (continued from fig.7). mla607 be bd bc bb ba b9 b8 b6 b7 b5 b4 b3 b2 b1 b0 ae af ad ac ab aa a9 a8 a6 a7 a5 a4 a3 a2 a1 a0 9e 9f 9d 9c 9b 9a 99 98 96 97 95 94 93 92 91 90 8e 8f 8d 8c 8b 8a 89 88 86 87 85 84 83 82 81 80 bit address register mnemonic direct byte address (hex) b8h b0h afh aeh adh ach abh aah a8h a0h 99h 98h 90h 8dh 8ch 8bh 8ah 89h 88h 87h 83h 82h 81h 80h sfrs containing directly addressable bits ip0 p3 p2 s0buf s0con p1 th1 th0 tl1 tl0 tmod pcon dph dpl sp p0 ien0 tcon a9h
1997 mar 14 16 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 10 i/o facilities 10.1 ports the p83cl78x has 32 i/o lines treated as 32 individually addressable bits or as four parallel 8-bit ports. to enable a port pin alternative function, the port bit latch in its sfr must contain a logic 1. the alternative functions are detailed below: port 0 provides the multiplexed low-order address and data bus for expanding the device with standard memories and peripherals. port 1 used for a number of special functions: provides the inputs for the eight external interrupts: int2 to int9 external activation of timer 2: t2 the i 2 c-bus interface: scl and sda. port 2 provides the high-order address when expanding the device with external program or data memory. port 3 pins can be configured individually to provide: external interrupt request inputs: int1 and int0 timer/counter inputs: t1 and t0 control signals to read and write to external memories: rd and wr uart asynchronous input and output (rxd and txd); or uart synchronous i/o and clock lines (data and clock).1 each port consists of a latch (sfrs p0 to p3), an output driver and input buffer. ports 1, 2 and 3 have internal pull-ups (except p1.6 and p1.7). figure 9(a) shows that the strong transistor p1 is turned on for only 2 oscillator periods after a low-to-high transition in the port latch. when on, it turns on p3 (a weak pull-up) through the inverter. this inverter and p3 form a latch which holds the logic 1. in port 0 the pull-up p1 is only on when emitting logic 1s for external memory access. writing a logic 1 to a port 1 bit latch leaves both output transistors switched off so that the pin can be used as an high-impedance input. 10.2 port options 30 of the 32 port pins (excluding p1.6 and p1.7 with option 2s only) may be individually configured with one of the following options. these options are also shown in fig.9. option 1 standard port; quasi-bidirectional i/o with pull-up. the strong booster pull-up p1 is turned on for two oscillator periods after a low-to-high transition in the port latch; fig.9(a). option 2 open-drain ; quasi-bidirectional i/o with n-channel open-drain output. use as an output requires the connection of an external pull-up resistor; fig.9(b). option 3 push-pull ; output with drive capability in both polarities. under this option, pins can only be used as outputs; fig.9(c). 10.3 port 0 options the definition of port options for port 0 is slightly different. two cases are considered. first, access to external memory ( ea = 0 or access above the built-in memory boundary) and second, i/o accesses. 10.3.1 e xternal memory accesses option 1 true logic 0 and logic 1 are written as address to the external memory (strong pull-up to be used). option 2 an external pull-up resistor is required for external accesses. option 3 not allowed for external memory accesses as the port can only be used as output. 10.3.2 i/o a ccesses option 1 when writing a logic 1 to the port latch, the strong pull-up p1 will be on for 2 oscillator periods. no weak pull-up exists. without an external pull-up, this option can be used as a high-impedance input. option 2 open-drain; quasi-directional i/o with n-channel open-drain output. use as an output requires the connection of an external pull-up resistor. see fig.9(b). option 3 push-pull; output with drive capability in both polarities. under this option pins can only be used as outputs. see fig.9(c). 10.4 set/reset options individual mask selection of the post-reset state is available with any of the above pins. the required selection is made by appending s or r to options 1, 2, or 3 above. option r reset, at reset this pin will be initialized low. option s set, at reset this pin will be initialized high.
1997 mar 14 17 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.9 port configuration options. handbook, full pagewidth mgd677 p1 n strong pull-up +5 v q from port latch (c) push-pull p1 p2 p3 input data read port pin 2 oscillator periods n strong pull-up i/o pin +5 v q from port latch input buffer (a) standard i/o pin n +5 v q from port latch input data read port pin input buffer (b) open-drain external pull-up i/o pin
1997 mar 14 18 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 11 timer/event counters the p83cl78x contains three 16-bit timer/event counter registers; timer 0, timer 1 and timer 2 which can perform the following functions: measure time intervals and pulse durations count events generate interrupt requests. in the timer operating mode the register is incremented every machine cycle. since a machine cycle consists of 12 oscillator periods, the count rate is 1 12 f osc . in the counter operating mode, the register is incremented in response to a high-to-low transition. since it takes 2 machine cycles (24 oscillator periods) to recognize a high-to-low transition, the maximum count rate is 1 24 f osc . to ensure a given level is sampled, it should be held for at least one complete machine cycle. 11.1 timer 0 and timer 1 timer 0 and timer 1 can be programmed independently to operate in four modes: mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. mode 1 16-bit time-interval or event counter. mode 2 8-bit time-interval or event counter with automatic reload upon overflow. mode 3 timer 0 establishes tl0 and th0 as two separate counters. 11.2 timer t2 timer t2 is a 16-bit timer/counter that can operate (like timer 0 and 1) either as a timer or as an event counter. these functions are selected by the state of the c/ t2 bit in the t2con register; see tables 1 and 2. three operating modes are available capture, auto-reload and baud rate generator, which also are selected via the t2con register; see table 3. 11.2.1 c apture mode figure 10 shows the capture mode. two options in this mode, may be selected by the exen2 bit in t2con: if exen2 = 0, then timer 2 is a 16-bit timer or counter which upon overflowing sets the timer 2 overflow bit tf2, this may then be used to generate an interrupt. if exen2 = 1, timer 2 operates as described above but with the additional feature that a high-to-low transition at external input t2ex causes the current value in tl2 and th2 to be captured into registers rcap2l and rcap2h respectively. in addition, the transition at t2ex causes the exf2 bit in t2con to be set; this may also be used to generate an interrupt. 11.2.2 a uto - reload mode figure 11 shows the auto-reload mode. also two options in this mode are selected by the exen2 bit in t2con: if exen2 = 0, then when timer 2 rolls over, it sets the tf2 bit but also causes the timer 2 registers to be reloaded with the 16-bit value held in registers rcap2l and rcap2h. the 16-bit value held in these registers is preset by software. if exen2 = 1, timer 2 operates as described above but with the additional feature that a high-to-low transition at external input t2ex will also trigger the 16-bit reload and set the exf2 bit. 11.2.3 b aud r ate g enerator mode the baud rate generator mode is selected when rtclk = 1. it will be described in conjunction with the serial port (uart); see section 14.3.2.
1997 mar 14 19 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 handbook, full pagewidth mla608 tl2 (8 bits) tr2 control th2 (8 bits) rcap2l rcap2h exf2 tf2 timer 2 interrupt exen2 control c/t2 = 1 t2 pin 12 osc transition detector t2ex pin c/t2 = 0 capture fig.10 timer 2 in capture mode. handbook, full pagewidth mla609 tl2 (8 bits) tr2 control th2 (8 bits) rcap2l rcap2h exf2 tf2 timer 2 interrupt exen2 control c/t2 = 0 c/t2 = 1 t2 pin 12 osc transition detector t2ex pin reload fig.11 timer 2 in auto-reload mode.
1997 mar 14 20 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 11.3 timer/counter 2 control register (t2con) table 1 timer/counter 2 control register (sfr address c8h) table 2 description of t2con bits table 3 timer 2 operating modes; x = dont care 76543210 tf2 exf2 gf2 rtclk exen2 tr2 c/ t2 cp/ rl2 bit symbol description 7 tf2 timer 2 over?ow ?ag . set by a timer 2 over?ow and must be cleared by software. tf2 will not be set when rtclk = 1. 6 exf2 timer 2 external ?ag. set when either a capture or reload is caused by a negative transition on t2ex and when exen2 = 1. when timer t2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to timer 2 interrupt routine. exf2 must be cleared by software. 5 gf2 general purpose ?ag bit. 4 rtclk receive/transmit clock ?ag . when set, causes the uart serial port to use timer 2 over?ow pulses for its receive and transmit clock in modes 1 and 3. rtclk = 0 causes timer 1 over?ows to be used for the receive and transmit clock. 3 exen2 timer 2 external enable ?ag . when set, allows a capture or reload to occur as a result of a negative transition on t2ex, if timer 2 is not being used to clock the serial port. exen2 = 0, causes timer 2 to ignore events at t2ex. 2 tr2 start/stop control for timer 2 . tr2 = 1 starts the timer. 1c/ t2 timer or counter select for timer 2 . c/ t2 = 0 selects the internal timer with a clock frequency of 1 12 f osc . c/ t2 = 1 selects the external event counter; negative edge triggered. 0 cp/ rl2 capture/reload ?ag . when set, captures will occur on negative transitions at t2ex, if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 over?ows or negative transitions at t2ex when exen2 = 1. when rtclk = 1, this bit is ignored and the timer is forced to auto-reload on a timer 2 over?ow. rtclk cp/ rl2 tr2 mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 x 1 baud rate generator xx0off
1997 mar 14 21 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 12 reduced power modes there are two software-selectable modes which further reduce power consumption: idle and power-down. 12.1 idle mode operation in idle mode permits the interrupt, serial ports and timer blocks to continue to function while the clock to the cpu is halted. idle mode is entered by setting the idl bit in the power control register (pcon.0, see table 5). the instruction that sets idl is the last instruction executed in the normal operating mode before the idle mode is activated. once in the idle mode, the cpu status is preserved along with the stack pointer, program counter, program status word and accumulator. the ram and all other registers maintain their data during idle mode. the status of the external pins during idle mode is shown in table 4. the following functions remain active during the idle mode: timer 0, timer 1 and timer 2 uart, i 2 c-bus interface external interrupt. these functions may generate an interrupt or reset; thus ending the idle mode. there are two ways to terminate the idle mode: 1. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware thus terminating the idle mode. the interrupt is serviced, and following the reti instruction, the next instruction to be executed will be the one following the instruction that put the device in the idle mode. the flag bits gf0 and gf1 may be used to determine whether the interrupt was received during normal execution or during the idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when the idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. 2. the second way of terminating the idle mode is with an external hardware reset, or an internal reset caused by an overflow of timer t2. since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 oscillator periods) to complete the reset operation. reset redefines all sfrs but does not affect the on-chip ram. 12.2 power-down mode operation in power-down mode freezes the oscillator. the internal connections which link both idle and power-down signals to the clock generation circuit are shown in fig.12. power-down mode is entered by setting the pd bit in the power control register (pcon.1, see table 5). the instruction that sets pd is the last executed prior to going into the power-down mode. once in the power-down mode, the oscillator is stopped. the contents of the on-chip ram and the sfrs are preserved. the port pins output the value held by their respective sfrs. ale and psen are held low. in the power-down mode, v dd may be reduced to minimize circuit power consumption. the supply voltage must not be reduced until the power-down mode is entered, and must be restored before the hardware reset is applied which will free the oscillator. reset should not be released until the oscillator has restarted and stabilized. 12.3 wake-up from power-down mode when in power-down mode the controller can be woken-up with either the external interrupts int2 to int9, or a reset operation. the wake-up operation has two basic approaches as explained in section 12.3.1; 12.3.2 and illustrated in fig.13. 12.3.1 w ake - up using int2 to int9 if any of the interrupts int2 to int9 are enabled, the device can be woken-up from the power-down mode with the external interrupts. to ensure that the oscillator is stable before the controller restarts, the internal clock will remain inactive for 1536 oscillator periods. this is controlled by an on-chip delay counter. 12.3.2 w ake - up using rst to wake-up the p83cl78x, the rst pin must be kept high for a minimum of 24 periods. the on-chip delay counter is inactive. the user must ensure that the oscillator is stable before any operation is attempted.
1997 mar 14 22 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 12.4 status of external pins the status of the external pins during idle and power-down mode is shown in table 4. if the power-down mode is activated whilst accessing external program memory, the port data that is held in the special function register p2 is restored to port 2. if the data is a logic 1, the port pin is held high during the power-down mode by the strong pull-up transistor p1; see fig.9(a). table 4 status of external pins during idle and power-down modes 12.5 power control register (pcon) the reduced power modes are activated by software using this special function register. pcon is not bit addressable. table 5 power control register (sfr address 87h) table 6 description of pcon bits note 1. if logic 1s are written to pd and idl at the same time, pd takes precedence. the reset value of pcon is (0xx00000). mode memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 port data port data port data port data idle external 1 1 ?oating port data address port data power-down internal 0 0 port data port data port data port data power-down external 0 0 ?oating port data port data port data 76543210 smod --- gf1 gf0 pd idl bit symbol function pcon.7 smod double baud rate bit. when set to a logic 1 the baud rate is doubled when the serial port sio0 is being used in modes 1, 2 or 3. pcon.6 - reserved pcon.5 - reserved pcon.4 - reserved pcon.3 gf1 general purpose ?ag bit pcon.2 gf0 general purpose ?ag bit pcon.1 pd power-down bit. setting this bit activates the power-down mode; see note 1. pcon.0 idl idle mode bit. setting this bit activates the idle mode; see note 1.
1997 mar 14 23 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.12 internal clock control in idle and power-down modes. handbook, full pagewidth mbb552 oscillator clock generator interrupts serial ports timer blocks cpu idl pd xtal1 xtal2 p83cl781 p83cl782 fig.13 wake-up operation. handbook, full pagewidth mgd679 delay counter 1536 periods 24 periods power-down rst pin external interrupt oscillator
1997 mar 14 24 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 13 i 2 c-bus serial i/o the serial port supports the twin line i 2 c-bus, which consists of a serial data line (sda) and a serial clock line (scl). these lines also function as the i/o port lines p1.7 and p1.6 respectively. the system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. the i 2 c-bus serial i/o has complete autonomy in byte handling and operates in 4 modes: master transmitter master receiver slave transmitter slave receiver. these functions are controlled by the serial control register s1con. s1sta is the status register whose contents may also be used as a vector to various service routines. s1dat is the data shift register and s1adr is the slave address register. slave address recognition is performed by on-chip hardware. figure 14 is the block diagram of the i 2 c-bus serial i/o. fig.14 block diagram of i 2 c-bus serial i/o. mlb199 slave address s1adr gc shift register s1dat sda arbitration sync logic scl bus clock generator s1sta internal bus 70 s1con 70 70 70 control register status register
1997 mar 14 25 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 13.1 serial control register (s1con) table 7 serial control register (sfr address d8h) table 8 description of s1con bits 76543210 cr2 ens1 sta sto si aa cr1 cr0 bit symbol description 7 cr2 this bit along with bits cr1 (s1con.1) and cr0 (s1con.0) determines the serial clock frequency when sio is in the master mode. see table 9. 6 ens1 enable serial i/o . when ens1 = 0, the serial i/o is disabled. sda and scl outputs are in the high impedance state; p1.6 and p1.7 function as open-drain ports. when ens1 = 1, the serial i/o is enabled. output port latches p1.6 and p1.7 must be set to logic 1. 5sta start ?ag . when this bit is set in slave mode, the sio hardware checks the status of the i 2 c-bus and generates a start condition if the bus is free or after the bus becomes free. if sta is set while the sio is in master mode, sio will generate a repeated start condition. 4sto stop ?ag . with this bit set while in master mode a stop condition is generated. when a stop condition is detected on the i 2 c-bus, the sio hardware clears the sto ?ag. sto may also be set in slave mode in order to recover from an error condition. in this case no stop condition is transmitted to the i 2 c-bus. however, the sio hardware behaves as if a stop condition has been received and releases the sda and scl. the sio then switches to the not addressed slave receiver mode. the stop ?ag is cleared by the hardware. 3si sio interrupt ?ag . this ?ag is set, and an interrupt is generated, after any of the following events occur: a start condition is generated in master mode own slave address has been received during aa = 1 the general call address has been received while gc (s1adr.0) = 1 and aa = 1 a data byte has been received or transmitted in master mode (even if arbitration is lost) a data byte has been received or transmitted as selected slave a stop or start condition is received as selected slave receiver or transmitter. 2aa assert acknowledge . when this bit is set, an acknowledge (low level to sda) is returned during the acknowledge clock pulse on the scl line when: own slave address is received general call address is received; gc (s1adr.0) = 1 a data byte is received while the device is programmed to be a master receiver a data byte is received while the device is a selected slave receiver. when this bit is reset, no acknowledge is returned. consequently, no interrupt is requested when the own slave address or general call address is received. 1 cr1 these two bits along with the cr2 (s1con.7) bit determine the serial clock frequency when sio is in the master mode. see table 9. 0 cr0
1997 mar 14 26 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 table 9 selection of the serial clock frequency scl in a master mode of operation 13.2 serial status register (s1sta) s1sta is a read-only register.the contents of this register may be used as a vector to a service routine. this optimizes the response time of the software and consequently that of the i 2 c-bus. the status codes for all possible modes of the i 2 c-bus interface are given in tables 12 to 16. table 10 serial status register (address d9h) table 11 description of s1sta bits table 12 mst/trx mode cr2 cr1 cr0 f osc divisor bit rate (khz) at f osc 3.58 mhz 6 mhz 12 mhz 0 0 0 256 14.0 23.4 46.9 0 0 1 224 16.0 26.8 53.6 0 1 0 192 18.6 31.3 62.5 0 1 1 160 22.4 37.5 75.0 1 0 0 960 3.73 6.25 12.5 1 0 1 120 29.8 50.0 100.0 1 1 0 60 59.7 100.0 - 1 1 1 not allowed --- 76543210 sc4 sc3 sc2 sc1 sc0 0 0 0 bit symbol description 3 to 7 sc4 to sc0 5-bit status code. 0 to 2 - these three bits are always zero. s1sta value description 08h a start condition has been transmitted. 10h a repeated start condition has been transmitted. 18h sla and w have been transmitted, ack has been received. 20h sla and w have been transmitted, ack received. 28h data of s1dat has been transmitted, ack received. 30h data of s1dat has been transmitted, ack received. 38h arbitration lost in sla, r/w or data.
1997 mar 14 27 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 table 13 mst/rec mode table 14 slv/rec mode table 15 slv/trx mode table 16 miscellaneous s1sta value description 08h a start condition has been transmitted. 10h a repeated start condition has been transmitted. 38h arbitration lost while returning ack. 40h sla and r have been transmitted, ack received. 48h sla and r have been transmitted, ack received. 50h data has been received, ack returned. 58h data has been received, ack returned. s1sta value description 60h own sla and w have been received, ack returned. 68h arbitration lost in sla, r/w as mst. own sla and w have been received, ack returned. 70h general call has been received, ack returned. 78h arbitration lost in sla, r/w as mst. general call has been received. 80h previously addressed with own sla. data byte received, ack returned. 88h previously addressed with own sla. data byte received, ack returned. 90h previously addressed with general call. data byte has been received, ack has been returned. 98h previously addressed with general call. data byte has been received, ack has been returned. a0h a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx. s1sta value description a8h own sla and r have been received, ack returned. b0h arbitration lost in sla, r/w as mst. own sla and r have been received, ack returned. b8h data byte has been transmitted, ack received. c0h data byte has been transmitted, ack received. c8h last data byte has been transmitted (aa = 0), ack received. s1sta value description 00h bus error during mst mode or selected slv mode, due to an erroneous start or stop condition. f8h no relevant state information available, si = 0.
1997 mar 14 28 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 table 17 symbols used in tables 12 to 16 13.3 data shift register (s1dat) s1dat contains the serial data to be transmitted or data which has just been received. the msb (bit 7) is transmitted or received first; i.e. data shifted from right to left. table 18 data shift register (sfr address dah) 13.4 address register (s1adr) this 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receiver/transmitter. table 19 address register (sfr address dbh) table 20 description of s1adr bits symbol description sla 7-bit slave address r read bit w write bit ack acknowledgement (acknowledge bit is logic 0) ack no acknowledgement (acknowledge bit is logic 1) data 8-bit data byte to or from i 2 c-bus mst master slv slave trx transmitter rec receiver 76543210 s1dat.7 s1dat.6 s1dat.5 s1dat.4 s1dat.3 s1dat.2 s1dat.1 s1dat.0 76543210 sla6 sla5 sla4 sla3 sla2 sla1 sla0 gc bit symbol description 7 to 1 sla6 to sla0 own slave address. 0 gc this bit is used to determine whether the general call address is recognized. when gc = 0, the general call address is not recognized; when gc = 1, the general call address is recognized.
1997 mar 14 29 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 14 standard serial interface sio0: uart this serial port is full duplex which means that it can transmit and receive simultaneously. it is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte has not been read by the time the reception of the second byte is complete, one of the bytes will be lost). the serial port receive and transmit registers are both accessed via the special function register s0buf. writing to s0buf loads the transmit register and reading s0buf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0 serial data enters and exits through rxd. txd outputs the shift clock. eight bits are transmitted/received (lsb first). the baud rate is fixed at 1 12 f osc . mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb first), and a stop bit (logic 1). on receive, the stop bit goes into rb8 in special function register s0con. the baud rate is variable. mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logic 0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (logic 1). on transmit, the 9 th data bit (tb8 in s0con) can be assigned the value of a logic 0 or logic 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9 th data bit goes into rb8 in s0con, while the stop bit is ignored. the baud rate is programmable to either 1 32 or 1 64 f osc . mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb first), a programmable 9 th data bit and a stop bit (logic 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses s0buf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. 14.1 multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9 th bit goes into rb8. the following bit is the stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated, but only if rb8 = 1. this feature is enabled by setting bit sm2 in s0con. one use of this feature, in multiprocessor systems, is as follows. when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9 th bit is high in an address byte and low in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be sent. the slaves that were not being addressed leave their sm2 bits set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
1997 mar 14 30 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 14.2 serial port control and status register (s0con) the serial port control and status register is the special function register s0con. the register contains not only the mode selection bits, but also the 9 th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). table 21 serial port control register (address 98h) table 22 description of s0con bits table 23 selection of the serial port modes 76543210 smo sm1 sm2 ren tb8 rb8 ti ri bit symbol description 7 sm0 these bits are used to select the serial port mode; see table 23. 6 sm1 5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in these modes, if sm2 = 1, then ri will not be activated if the received 9 th data bit (rb8) is a logic 0. in mode 1, if sm2 = 1, then ri will not be activated unless a valid stop bit was received. in mode 0, sm2 should be a logic 0. 4 ren enables serial reception and is set by software to enable reception, and cleared by software to disable reception. 3 tb8 is the 9 th data bit that will be transmitted in modes 2 and 3. set or cleared by software as desired. 2 rb8 in modes 2 and 3, is the 9 th data bit received. in mode 1, if sm2 = 0 then rb8 is the stop bit that was received. in mode 0, rb8 is not used. 1ti the transmit interrupt ?ag . set by hardware at the end of the 8 th bit time in mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. must be cleared by software. 0ri the receive interrupt ?ag . set by hardware at the end of the 8 th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (except see sm2). must be cleared by software. smo sm1 mode description baud rate 0 0 mode 0 shift register 1 12 f osc 0 1 mode 1 8-bit uart variable 1 0 mode 2 9-bit uart 1 32 or 1 64 f osc 1 1 mode 3 9-bit uart variable
1997 mar 14 31 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 14.3 baud rates the baud rate in mode 0 is fixed and may be calculated as: the baud rate in mode 2 depends on the value of the smod bit in special function register pcon and may be calculated as: if smod = 0 (value on reset), the baud rate is 1 64 f osc if smod = 1, the baud rate is 1 32 f osc the baud rates in modes 1 and 3 are determined by the timer 1 or timer 2 overflow rate. 14.3.1 u sing t imer 1 to generate baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of the smod bit as follows: baud rate f osc 12 -------- = baud rate 2 smod 64 ---------------- - f osc = baud rate 2 smod 32 ---------------- - timer 1 overflow rate. = the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either timer or counter operation in any of its 3 running modes. in most typical applications, it is configured for timer operation, in the auto-reload mode (high nibble of tmod = 0010b). in this case the baud rate is given by the formula: by configuring timer 1 to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload, very low baud rates can be achieved. table 24 lists commonly used baud rates and how they can be obtained from timer 1. baud rate 2 smod 32 ---------------- - f osc 12 256 th1 C () {} -------------------------------------------------------- = table 24 commonly used baud rates generated by timer 1 notes 1. maximum in mode 0. 2. x = dont care. 3. maximum in mode 2. 4. maximum in modes 1 and 3. baud rate (kb/s) f osc (mhz) smod c/t timer 1 mode reload value 1000.0 (1) 12.000 x (2) xx x 375.0 (3) 12.000 1 x x x 62.5 (4) 12.000 1 0 mode 2 ffh 19.2 11.059 1 0 mode 2 fdh 9.6 11.059 0 0 mode 2 fdh 4.8 11.059 0 0 mode 2 fah 2.4 11.059 0 0 mode 2 f4h 1.2 11.059 0 0 mode 2 e8h 137.5 11.986 0 0 mode 2 1dh 110.0 6.000 0 0 mode 2 72h 110.0 12.000 0 0 mode 1 feebh
1997 mar 14 32 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 14.3.2 u sing t imer 2 to generate baud rates timer 2 is selected as a baud rate generator by setting the rtclk bit in t2con. the baud rate generator mode is similar to the auto-reload mode, in that a roll-over in th2 causes timer 2 registers to be reloaded with the 16-bit value held in the registers rcap2h and rcap2l, which are preset by software. baud rates in modes 1 and 3 are determined by timer 2's overflow rate as specified below. the timer 2 can be configured for either timer or counter operation. in the most typical applications, it is configured for timer operation (c/ t2 = 0). timer operation is slightly different for timer 2 when it is being used as a baud rate generator. normally, as a timer it would increment every machine cycle at a frequency of 1 12 f osc . however, as a baud rate generator it increments every state time at a frequency of 1 2 f osc . in this case the baud rate in modes 1 and 3 is determined as: baud rate timer 2 overflow rate 16 ----------------------------------------------------------- - = baud rate f osc 32 65536 rcap2h; rcap2l () C {} ---------------------------------------------------------------------------------------------------- - - = where (rcap2h; rcap2l) is the content of registers rcap2h and rcap2l taken as a 16-bit unsigned integer. the baud rate generator mode for timer 2 is shown in fig.15. this figure is only valid if rtclk = 1. at roll-over th2 does not set the tf2 bit in t2con and therefore, will not generate an interrupt. consequently, the timer 2 interrupt does not need to be disabled when in the baud rate generator mode. if exen2 is set, a high-to-low transition on t2ex will set the exf2 bit, also in t2con, but will not cause a reload from (rcap2h; rcap2l) to (th2, tl2). therefore, in this mode t2ex may be used as an additional external interrupt. when timer 2 is operating as a timer (tr2 = 1), in the baud rate generator mode, registers th2 and tl2 should not be accessed (read or write). under these conditions the timer is being incremented every state time and therefore the results of a read or write may not be accurate. the registers rcap2h and rcap2l however, may be read but not written to. a write might overlap a reload and cause write and/or reload errors. if a write operation is required, timer 2 or rcap2h/rcap2l should first be turned off by clearing the tr2 bit. handbook, full pagewidth mgd622 tl2 (8 bits) tr2 control th2 (8 bits) rcap2l rcap2h exf2 exen2 control c/t2 = 0 c/t2 = 1 t2 pin 2 osc transition detector t2ex pin timer 2 interrupt (additional external interrupt) (note: divided by 2 not by 12) 16 rtclk reload clk uart receive/ transmit clock smod 10 1 0 2 timer 1 overflow fig.15 timer 2 in baud rate generator mode.
1997 mar 14 33 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.16 serial port mode 0. handbook, full pagewidth mgc752 start shift t1 tx control tx clock send serial port interrupt rx clock r1 shift rx control start input shift register s0 buffer internal bus read sbuf shift load sbuf s0 buffer zero detector shift d cl s q internal bus write to sbuf 11111110 ren s6 ri rxd p3.0 alt output function receive shift clock txd p3.1 alt output function rxd p3.0 alt input function
1997 mar 14 34 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 handbook, full pagewidth mla567 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 ...s6 write to sbuf s6p2 d0 d1 d2 d3 d4 d5 d6 d7 s3p1 s6p1 write to scon (clear r1) d0 d1 d2 d3 d4 d5 d6 d7 s5p2 ale send shift rxd (data out) tsc (shift clock) ri receive shift rxd (data in) txd (shift clock) t r a n s m i t r e c e i v e fig.17 serial port mode 0 timing.
1997 mar 14 35 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 handbook, full pagewidth mgc755 start shift data t1 tx control tx clock send 16 serial port interrupt 16 rx clock r1 load sbuf shift rx control start sample input shift register (9-bits) bit detector s0 buffer internal bus read sbuf shift load sbuf s0 buffer zero detector shift d cl s q tb8 internal bus write to sbuf rxd txd 0 smod rtclk 1 01 high-to-low transition detector 2 timer 1 overflow timer 2 overflow fig.18 serial port mode 1.
1997 mar 14 36 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.19 serial port mode 1 timing. handbook, full pagewidth mla569 d0 d1 d2 d3 d4 d5 d6 d7 start bit d0 d1 d2 d3 d4 d5 d6 d7 tx clock write to sbuf data shift txd ti start bit s1p1 stop bit 16 reset rx clock rxd stop bit bit detector sample time shift ri send t r a n s m i t r e c e i v e
1997 mar 14 37 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.20 serial port mode 2. handbook, full pagewidth mgc754 start stop bit shift data t1 tx control tx clock send 16 serial port interrupt 16 rx clock r1 load sbuf shift rx control start sample input shift register (9-bits) bit detector s0 buffer internal bus read sbuf shift load sbuf s0 buffer zero detector shift d cl s q tb8 internal bus write to sbuf 2 phase 2 clock (f osc / 2) rxd txd 0 csmod at pcon.7 1 high-to-low transition detector
1997 mar 14 38 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 handbook, full pagewidth tx clock stop bit gen rx clock bit detector sample time shift mla571 d0 d1 d2 d3 d4 d5 d6 d7 tb8 write to sbuf send data shift txd ti start bit s1p1 stop bit 16 reset start bit rxd d0 d1 d2 d3 d4 d5 d6 d7 stop bit ri rb8 t r a n s m i t r e c e i v e fig.21 serial port mode 2 timing.
1997 mar 14 39 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.22 serial port mode 3. handbook, full pagewidth mgc753 start shift data t1 0 smod rtclk 1 01 tx control tx clock send 16 serial port interrupt 16 rx clock r1 load sbuf shift rx control start high-to-low transition detector sample input shift register (9-bits) bit detector s0 buffer internal bus read sbuf shift load sbuf s0 buffer zero detector shift d cl s q tb8 internal bus write to sbuf 2 timer 1 overflow timer 2 overflow rxd txd
1997 mar 14 40 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.23 serial port mode 3 timing. handbook, full pagewidth mla573 d0 d1 d2 d3 d4 d5 d6 d7 tx clock write to sbuf send data shift txd ti start bit s1p1 stop bit 16 reset start bit rx clock rxd d0 d1 d2 d3 d4 d5 d6 d7 stop bit bit detector sample time shift ri tb8 tb8 t r a n s m i t r e c e i v e
1997 mar 14 41 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 15 interrupt system external events and the real-time-driven on-chip peripherals require service by the cpu at unpredictable times. to tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. the system is shown in fig.24. the p83cl78x acknowledges interrupt requests from fifteen sources as follows: int0 to int9 timer 0, timer 1 and timer 2 i 2 c-bus serial i/o uart. each interrupt vectors to a separate location in program memory for its service routine. each source can be individually enabled or disabled by its corresponding bit in the interrupt enable registers (ien0 and ien1). the priority level is selected via the interrupt priority registers (ip0 and ip1). all enabled sources can be globally disabled or enabled. 15.1 external interrupts int2 to int9 port 1 lines serve an alternative purpose as eight additional interrupts int2 to int9. when enabled, each of these lines may wake-up the device from the power-down mode. using the interrupt polarity register (ix1), each pin may be initialized to be either active high or active low. irq1 is the interrupt request flag register. if the interrupt is enabled, each flag will be set on an interrupt request but must be cleared by software, i.e. via the interrupt software or when the interrupt is disabled. port 1 interrupts are level-sensitive. a port 1 interrupt will be recognized when a level (high or low depending on the interrupt polarity register) on p1.n is held active for at least one machine cycle. the interrupt request is not serviced until the next machine cycle. figure 25 shows the external interrupt system. 15.2 interrupt priority each interrupt source can be set to either a high priority or to a low priority. if a low priority interrupt is received simultaneously with a high priority interrupt, the high priority interrupt will be dealt with first. if interrupts of the same priority are requested simultaneously, the processor will branch to the interrupt polled first, according to the sequence shown in table 25 and in fig.24. the vector address is the rom location where the appropriate interrupt service routine starts. table 25 interrupt vector polling sequence a low priority interrupt routine can only be interrupted by a high priority interrupt. a high priority interrupt routine cannot be interrupted. symbol vector address (hex) source x0 (?rst) 0003 external 0 s1 002b i 2 c port x5 0053 external 5 t0 000b timer 0 t2 0033 timer 2 x6 005b external 6 x1 0013 external 1 x2 003b external 2 x7 0063 external 7 t1 001b timer 1 x3 0043 external 3 x8 006b external 8 so 0023 uart x4 004b external 4 x9 (last) 0073 external 9
1997 mar 14 42 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.24 interrupt system. interrupt sources registers priority global enable x0 s1 x5 t0 t2 x6 x1 x2 x7 t1 x3 x8 s0 ien0/1 ip0/1 high low interrupt polling sequence mla611 x4 x9
1997 mar 14 43 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 15.3 interrupt registers the registers used in the interrupt system are listed in table 26. tables 27 to 38 describe the contents of these registers. table 26 special function registers related to the interrupt system address register description a8h ien0 interrupt enable register e8h ien1 interrupt enable register (int2 to int9) b8h ip0 interrupt priority register f8h ip1 interrupt priority register (int2 to int9) e9h ix1 interrupt polarity register c0h irq1 interrupt request flag register fig.25 external interrupt configuration. handbook, full pagewidth mla575 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 x9 x8 x7 x6 x5 x4 x3 x2 ix1 ien1 irq1 wake-up
1997 mar 14 44 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 15.3.1 i nterrupt e nable r egister (ien0) bit values: 0 = interrupt disabled; 1 = interrupt enabled. table 27 interrupt enable register (sfr address a8h) table 28 description of ien0 bits 15.3.2 i nterrupt e nable r egister (ien1) bit values: 0 = interrupt disabled; 1 = interrupt enabled. table 29 interrupt enable register (sfr address e8h) table 30 description of ien1 bits 76543210 ea et2 es1 es0 et1 ex1 et0 ex0 bit symbol description 7 ea general enable/disable control. if ea = 0, no interrupt is enabled. if ea = 1, any individually enabled interrupt will be accepted. 6 et2 enable t2 interrupt 5 es1 enable i 2 c interrupt 4 es0 enable uart sio interrupt 3 et1 enable timer 1 interrupt (t1) 2 ex1 enable external interrupt 1 1 et0 enable timer 0 interrupt (t0) 0 ex0 enable external interrupt 0 76543210 ex9 ex8 ex7 ex6 ex5 ex4 ex3 ex2 bit symbol description 7 ex9 enable external interrupt 9 6 ex8 enable external interrupt 8 5 ex7 enable external interrupt 7 4 ex7 enable external interrupt 6 3 ex5 enable external interrupt 5 2 ex4 enable external interrupt 4 1 ex3 enable external interrupt 3 0 ex2 enable external interrupt 2
1997 mar 14 45 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 15.3.3 i nterrupt p riority r egister (ip0) bit values: 0 = low priority; 1 = high priority. table 31 interrupt priority register (sfr address b8h) table 32 description of ip0 bits 15.3.4 i nterrupt p riority r egister (ip1) bit values: 0 = low priority; 1 = high priority. table 33 interrupt priority register (sfr address f8h) table 34 description of ip1 bits 76543210 - pt2 ps1 ps0 pt1 px1 pt0 px0 bit symbol description 7 - reserved 6 pt2 timer 2 interrupt priority level 5 ps1 i 2 c interrupt priority level 4 ps0 uart sio interrupt priority level 3 pt1 timer 1 interrupt priority level 2 px1 external interrupt 1 priority level 1 pt0 timer 0 interrupt priority level 0 px0 external interrupt 0 priority level 76543210 px9 px8 px7 px6 px5 px4 px3 px2 bit symbol description 7 px9 external interrupt 9 priority level 6 px8 external interrupt 8 priority level 5 px7 external interrupt 7 priority level 4 px6 external interrupt 6 priority level 3 px5 external interrupt 5 priority level 2 px4 external interrupt 4 priority level 1 px3 external interrupt 3 priority level 0 px2 external interrupt 2 priority level
1997 mar 14 46 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 15.3.5 i nterrupt p olarity r egister (ix1) writing either a logic 1 or logic 0 to any interrupt polarity register bit sets the polarity level of the corresponding external interrupt to an active high or active low respectively. table 35 interrupt polarity register (sfr address e9h) table 36 description of ix1 bits 15.3.6 i nterrupt r equest f lag r egister (irq1) table 37 interrupt request flag register (sfr address c0h) table 38 description of irq1 bits 76543210 il9 il8 il7 il6 il5 il4 il3 il2 bit symbol description 7 il9 external interrupt 9 polarity level 6 il8 external interrupt 8 polarity level 5 il7 external interrupt 7 polarity level 4 il6 external interrupt 6 polarity level 3 il5 external interrupt 5 polarity level 2 il4 external interrupt 4 polarity level 1 il3 external interrupt 3 polarity level 0 il2 external interrupt 2 polarity level 76543210 iq9 iq8 iq7 iq6 iq5 iq4 iq3 iq2 bit symbol description 7 iq9 external interrupt 9 request ?ag 6 iq8 external interrupt 8 request ?ag 5 iq7 external interrupt 7 request ?ag 4 iq6 external interrupt 6 request ?ag 3 iq5 external interrupt 5 request ?ag 2 iq4 external interrupt 4 request ?ag 1 iq3 external interrupt 3 request ?ag 0 iq2 external interrupt 2 request ?ag
1997 mar 14 47 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 16 oscillator circuitry the on-chip oscillator circuitry of the p8xcl580 is a single-stage inverting amplifier biased by an internal feedback resistor. the oscillator circuit is shown in fig.26. for operation as a standard quartz oscillator, no external components are needed, except for the 32 khz option. when using external capacitors, ceramic resonators, coils and rc networks to drive the oscillator, five different configurations are supported (see table 39 and fig.26). in the power-down mode the oscillator is stopped and xtal1 is pulled high. the oscillator inverter is switched off to ensure no current will flow regardless of the voltage at xtal1, for configurations (a), (b), (c), (d), (e) and (g) of fig.26. to drive the device with an external clock source, apply the external clock signal to xtal1, and leave xtal2 to float, as shown in fig.26(f). there are no requirements on the duty cycle of the external clock, since the input to the internal clocking circuitry is buffered by a flip-flop. various oscillator options are provided for optimum on-chip oscillator performance; these are specified in table 40 and shown in fig.26. the required option should be stated when ordering. table 39 oscillator options option application oscillator 1 for 32 khz clock applications with external trimmer for frequency adjustment. a 4.7 m w bias resistor is needed for use in parallel with the crystal; see fig.26(c). oscillator 2 low-power, low-frequency operations using lc components; see fig.26(e). oscillator 3 medium frequency range applications. oscillator 4 high frequency range applications. rc oscillator rc oscillator con?guration; see figs 26(g) and 28. h andbook, full pagewidth mla577 v dd xtal1 xtal2 (d) xtal1 xtal2 (e) xtal1 xtal2 (f) xtal1 xtal2 (g) n.c. n.c. xtal1 xtal2 (b) xtal1 xtal2 (c) xtal1 xtal2 (a) standard quartz oscillator quartz oscillator with external capacitors 32 khz oscillator ceramic resonator lc - oscillator external clock rc - oscillator fig.26 oscillator configurations.
1997 mar 14 48 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.27 standard oscillator. mla613 v dd p83cl781 p83cl782 v dd r bias c1 i c2 i xtal1 xtal2 to internal timing circuits v dd pd fig.28 rc oscillator; frequency as a function of rc. handbook, halfpage 0 600 400 200 0 246 mla579 rc ( m s) (khz) f osc rc oscillator frequency is externally adjustable; 100 khz f osc 500 khz.
1997 mar 14 49 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 table 40 oscillator type selection guide note 1. 32 khz quartz crystals with a series resistance >15 k w will reduce the guaranteed supply voltage range to 2.5 to 3.5 v. resonator frequency (mhz) option (see table 39) c1 ext. (pf) c2 ext. (pf) resonator max. series resistance min. max. min. max. quartz 0.032 oscillator 1 0 0 5 15 15 k w ; note 1 1.0 oscillator 2 030030 600 w 3.58 0 15 0 15 100 w 4.0 020020 75 w 6.0 oscillator 3 0 10 0 10 60 w 10.0 oscillator 4 015015 60 w 12.0 0 10 0 10 40 w 16.0 0 15 0 15 20 w pxe 0.455 oscillator 2 40 50 40 50 10 w 1.0 15 50 15 50 100 w 3.58 0 40 0 40 10 w 4.0 040040 10 w 6.0 020020 5 w 10.0 oscillator 3 0 15 0 15 6 w 12.0 oscillator 4 10 40 10 40 6 w lc oscillator 2 20 90 20 90 10 m h=1 w 100 m h=5 w 1 mh = 75 w
1997 mar 14 50 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 table 41 oscillator equivalent circuit parameters the equivalent circuit data of the internal oscillator compares with that of matched crystals. symbol parameter option condition min. typ. max. unit g m transconductance oscillator 1; 32 khz t amb = +25 c; v dd = 4.5 v - 15 -m s oscillator 2 200 600 1000 m s oscillator 3 400 1500 4000 m s oscillator 4 1000 4000 10000 m s c1 i input capacitance oscillator 1; 32 khz - 3.0 - pf oscillator 2 - 8.0 - pf oscillator 3 - 8.0 - pf oscillator 4 - 8.0 - pf c2 i output capacitance oscillator 1; 32 khz - 23 - pf oscillator 2 - 8.0 - pf oscillator 3 - 8.0 - pf oscillator 4 - 8.0 - pf r2 output resistance oscillator 1; 32 khz - 3800 - k w oscillator 2 - 65 - k w oscillator 3 - 18 - k w oscillator 4 - 5.0 - k w fig.29 oscillator equivalent circuit diagram. handbook, full pagewidth mla578 c1 i r f v 1 g m c2 i r 2 xtal1 xtal2
1997 mar 14 51 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 17 reset to initialize the p83cl78x a reset is performed by either of two methods: applying an external signal to the rst pin via power-on reset circuitry. the reset state of the port pins is mask-programmable and can be defined by the user. the standard reset value for ports 0 to 3 is ffh. a reset leaves the internal registers as shown in chapter 18. 17.1 external reset using the rst pin the reset input for the p83cl78x is rst. a schmitt trigger is used at the input for noise rejection. the output of the schmitt trigger is sampled by the reset circuitry every machine cycle. a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running. the cpu responds by executing an internal reset. port pins adopt their reset state immediately after the rst goes high. during reset, ale and psen are held high. the external reset is asynchronous to the internal clock. the rst pin is sampled during state 5, phase 2 of every machine cycle. after a high is detected at the rst pin, an internal reset is repeated until rst goes low. the internal ram is not affected by reset. when v dd is turned on, the ram contents are indeterminate. 17.2 power-on reset the device contains on-chip circuitry which switches the port pins to the customer defined logic level as soon as v dd exceeds 1.3 v; if the mask option on has been chosen. as soon as the minimum supply voltage is reached, the oscillator will start up. however, to ensure that the oscillator is stable before the controller starts, the clock signals are gated away from the cpu for a further 1536 oscillator periods. a hysteresis of approximately 50 mv at a typical power-on switching level of 1.3 v will ensure correct operation. see fig.32. the on-chip power-on reset circuitry can also be switched off via the mask option off. this option reduces the power-down current to typically 800 na and can be chosen if external reset circuitry is used. for applications not requiring the internal reset, option off should be chosen. an automatic reset can be obtained by connecting the rst pin to v dd via a 10 m f capacitor. at power-on, the voltage on the rst pin is equal to v dd minus the capacitor voltage, and decreases from v dd as the capacitor charges through the internal resistor (r rst ) to ground. the larger the capacitor, the more slowly v rst decreases. v rst must remain above the lower threshold of the schmitt trigger long enough to effect a complete reset. the time required is the oscillator start-up time, plus 2 machine cycles. the power-on reset circuitry is shown in fig.31. fig.30 reset configuration. handbook, halfpage mla580 schmitt trigger reset circuitry rst fig.31 power-on reset circuitry. v dd v dd rst 10 m f r rst mla612 p83cl781 p83cl782
1997 mar 14 52 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.32 power-on reset switching level. handbook, full pagewidth mla581 supply voltage power-on-reset (internal) oscillator cpu running start-up time 1536 oscillator periods delay hysteresis switching level por
1997 mar 14 53 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 18 special function registers overview the p83cl78x has 34 sfrs available to the user. notes 1. bit addressable register. 2. port reset state determined by the customer. address (hex) name reset value (b) function f8 ip1 (1) 00000000 interrupt priority register (int2 to int9) f0 b (1) 00000000 b register e9 ix1 00000000 interrupt polarity register e8 ien1 (1) 00000000 interrupt enable register 1 e0 acc (1) 00000000 accumulator db s1adr 00000000 i 2 c-bus slave address register da s1dat 00000000 i 2 c-bus data shift register d9 s1sta 11111000 i 2 c-bus serial status register d8 s1con (1) 00000000 i 2 c-bus serial control register d0 psw (1) 00000000 program status word cd th2 00000000 timer 2 high byte cc tl2 00000000 timer 2 low byte cb rcap2h 00000000 timer 2 reload/capture register high byte ca rcap2l 00000000 timer 2 reload/capture register low byte c8 t2con (1) 00000000 timer/counter 2 control register c0 irq1 (1) 00000000 interrupt request flag register b8 ip0 (1) x 0000000 interrupt priority register 0 b0 p3 (1) xxxxxxxx (2) digital i/o port register 3 a8 ien0 (1) 00000000 interrupt enable register a0 p2 (1) xxxxxxxx (2) digital i/o port register 2 99 s0buf xxxxxxxx serial data buffer register 0 98 s0con (1) 00000000 serial port control register 0 90 p1 (1) xxxxxxxx (2) digital i/o port register 1 8d th1 00000000 timer 1 high byte 8c th0 00000000 timer 0 high byte 8b tl1 00000000 timer 1 low byte 8a tl0 00000000 timer 0 low byte 89 tmod 00000000 timer 0 and 1 mode control register 88 tcon (1) 00000000 timer 0 and 1 control/external interrupt control register 87 pcon 0xx00000 power control register 83 dph 00000000 data pointer high byte 82 dpl 00000000 data pointer low byte 81 sp 00000111 stack pointer 80 p0 (1) xxxxxxxx (2) digital i/o port register 0
1997 mar 14 54 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 19 instruction set the p83cl78x uses a powerful instruction set which permits the expansion of on-chip cpu peripherals and optimizes byte efficiency and execution speed. assigned opcodes add new high-power operation and permit new addressing modes. the instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. when using a 12 mhz oscillator, 64 instructions execute in 1 m s and 45 instructions execute in 2 m s. multiply and divide instructions execute in 4 m s. for the description of the data addressing modes and hexadecimal opcode cross-reference see table 46. table 42 instruction set description: arithmetic operations mnemonic description bytes cycles opcode (hex) arithmetic operations add a,rr add register to a 1 1 2* add a,direct add direct byte to a 2 1 25 add a,@ri add indirect ram to a 1 1 26, 27 add a,#data add immediate data to a 2 1 24 addc a,rr add register to a with carry ?ag 1 1 3* addc a,direct add direct byte to a with carry ?ag 2 1 35 addc a,@ri add indirect ram to a with carry ?ag 1 1 36, 37 addc a,#data add immediate data to a with carry ?ag 2 1 34 subb a,rr subtract register from a with borrow 1 1 9* subb a,direct subtract direct byte from a with borrow 2 1 95 subb a,@ri subtract indirect ram from a with borrow 1 1 96, 97 subb a,#data subtract immediate data from a with borrow 2 1 94 inc a increment a 1 1 04 inc rr increment register 1 1 0* inc direct increment direct byte 2 1 05 inc @ri increment indirect ram 1 1 06, 07 dec a decrement a 1 1 14 dec rr decrement register 1 1 1* dec direct decrement direct byte 2 1 15 dec @ri decrement indirect ram 1 1 16, 17 inc dptr increment data pointer 1 2 a3 mul ab multiply a and b 1 4 a4 div ab divide a by b 1 4 84 da a decimal adjust a 1 1 d4
1997 mar 14 55 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 table 43 instruction set description: logic operations mnemonic description bytes cycles opcode (hex) logic operations anl a,rr and register to a 1 1 5* anl a,direct and direct byte to a 2 1 55 anl a,@ri and indirect ram to a 1 1 56, 57 anl a,#data and immediate data to a 2 1 54 anl direct,a and a to direct byte 2 1 52 anl direct,#data and immediate data to direct byte 3 2 53 orl a,rr or register to a 1 1 4* orl a,direct or direct byte to a 2 1 45 orl a,@ri or indirect ram to a 1 1 46, 47 orl a,#data or immediate data to a 2 1 44 orl direct,a or a to direct byte 2 1 42 orl direct,#data or immediate data to direct byte 3 2 43 xrl a,rr exclusive-or register to a 1 1 6* xrl a,direct exclusive-or direct byte to a 2 1 65 xrl a,@ri exclusive-or indirect ram to a 1 1 66, 67 xrl a,#data exclusive-or immediate data to a 2 1 64 xrl direct,a exclusive-or a to direct byte 2 1 62 xrl direct,#data exclusive-or immediate data to direct byte 3 2 63 clr a clear a 1 1 e4 cpl a complement a 1 1 f4 rl a rotate a left 1 1 23 rlc a rotate a left through the carry ?ag 1 1 33 rr a rotate a right 1 1 03 rrc a rotate a right through the carry ?ag 1 1 13 swap a swap nibbles within a 1 1 c4
1997 mar 14 56 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 table 44 instruction set description: data transfer note 1. mov a,acc is not permitted. mnemonic description bytes cycles opcode (hex) data transfer mov a,rr move register to a 1 1 e* mov a,direct (note 1) move direct byte to a 2 1 e5 mov a,@ri move indirect ram to a 1 1 e6, e7 mov a,#data move immediate data to a 2 1 74 mov rr,a move a to register 1 1 f* mov rr,direct move direct byte to register 2 2 a* mov rr,#data move immediate data to register 2 1 7* mov direct,a move a to direct byte 2 1 f5 mov direct,rr move register to direct byte 2 2 8* mov direct,direct move direct byte to direct 3 2 85 mov direct,@ri move indirect ram to direct byte 2 2 86, 87 mov direct,#data move immediate data to direct byte 3 2 75 mov @ri,a move a to indirect ram 1 1 f6, f7 mov @ri,direct move direct byte to indirect ram 2 2 a6, a7 mov @ri,#data move immediate data to indirect ram 2 1 76, 77 mov dptr,#data 16 load data pointer with a 16-bit constant 3 2 90 movc a,@a+dptr move code byte relative to dptr to a 1 2 93 movc a,@a+pc move code byte relative to pc to a 1 2 83 movx a,@ri move external ram (8-bit address) to a 1 2 e2, e3 movx a,@dptr move external ram (16-bit address) to a 1 2 e0 movx @ri,a move a to external ram (8-bit address) 1 2 f2, f3 movx @dptr,a move a to external ram (16-bit address) 1 2 f0 push direct push direct byte onto stack 2 2 c0 pop direct pop direct byte from stack 2 2 d0 xch a,rr exchange register with a 1 1 c* xch a,direct exchange direct byte with a 2 1 c5 xch a,@ri exchange indirect ram with a 1 1 c6, c7 xchd a,@ri exchange low-order digit indirect ram with a 1 1 d6, d7
1997 mar 14 57 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 table 45 instruction set description: boolean variable manipulation, program and machine control mnemonic description bytes cycles opcode (hex) boolean variable manipulation clr c clear carry ?ag 1 1 c3 clr bit clear direct bit 2 1 c2 setb c set carry ?ag 1 1 d3 setb bit set direct bit 2 1 d2 cpl c complement carry ?ag 1 1 b3 cpl bit complement direct bit 2 1 b2 anl c,bit and direct bit to carry ?ag 2 2 82 anl c,/bit and complement of direct bit to carry ?ag 2 2 b0 orl c,bit or direct bit to carry ?ag 2 2 72 orl c,/bit or complement of direct bit to carry ?ag 2 2 a0 mov c,bit move direct bit to carry ?ag 2 1 a2 mov bit,c move carry ?ag to direct bit 2 2 92 program and machine control acall addr11 absolute subroutine call 2 2 1 lcall addr16 long subroutine call 3 2 12 ret return from subroutine 1 2 22 reti return from interrupt 1 2 32 ajmp addr11 absolute jump 2 2 1 ljmp addr16 long jump 3 2 02 sjmp rel short jump (relative address) 2 2 80 jmp @a+dptr jump indirect relative to the dptr 1 2 73 jz rel jump if a is zero 2 2 60 jnz rel jump if a is not zero 2 2 70 jc rel jump if carry ?ag is set 2 2 40 jnc rel jump if carry ?ag is not set 2 2 50 jb bit,rel jump if direct bit is set 3 2 20 jnb bit,rel jump if direct bit is not set 3 2 30 jbc bit,rel jump if direct bit is set and clear bit 3 2 10 cjne a,direct,rel compare direct to a and jump if not equal 3 2 b5 cjne a,#data,rel compare immediate to a and jump if not equal 3 2 b4 cjne rr,#data,rel compare immediate to register and jump if not equal 3 2 b* cjne @ri,#data,rel compare immediate to indirect and jump if not equal 3 2 b6, b7 djnz rr,rel decrement register and jump if not zero 2 2 d* djnz direct,rel decrement direct and jump if not zero 3 2 d5 nop no operation 1 1 00
1997 mar 14 58 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 table 46 description of the mnemonics in the instruction set mnemonic description data addressing modes rr working register r0-r7. direct 128 internal ram locations and any special function register (sfr). @ri indirect internal ram location addressed by register r0 or r1 of the actual register bank. #data 8-bit constant included in instruction. #data 16 16-bit constant included as bytes 2 and 3 of instruction. bit direct addressed bit in internal ram or sfr. addr16 16-bit destination address. used by lcall and ljmp. the branch will be anywhere within the 64 kbytes program memory address space. addr11 111-bit destination address. used by acall and ajmp. the branch will be within the same 2 kbytes page of program memory as the ?rst byte of the following instruction. rel signed (two's complement) 8-bit offset byte. used by sjmp and all conditional jumps. range is - 128 to +127 bytes relative to ?rst byte of the following instruction. hexadecimal opcode cross-reference * 8, 9, a, b, c, d, e, f. 1, 3, 5, 7, 9, b, d, f. 0, 2, 4, 6, 8, a, c, e.
1997 mar 14 59 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 table 47 instruction map note 1. mov a, acc is not a valid instruction. first hexadecimal character of opcode ? second hexadecimal character of opcode ? 0123 456789abcdef 0 nop ajmp addr11 ljmp addr16 rr a inc a inc direct inc @ri inc rr 0 1 01234567 1 jbc bit,rel acall addr11 lcall addr16 rrc a dec a dec direct dec @ri dec rr 0 1 01234567 2 jb bit,rel ajmp addr11 ret rl a add a,#data add a,direct add a,@ri add a,rr 0 1 01234567 3 jnb bit,rel acall addr11 reti rlc a addc a,#data addc a,direct addc a,@ri addc a,rr 0 1 01234567 4 jc rel ajmp addr11 orl direct,a orl direct,#data orl a,#data orl a,direct orl a,@ri orl a,rr 0 1 01234567 5 jnc rel acall addr11 anl direct,a anl direct,#data anl a,#data anl a,direct anl a,@ri anl a,rr 0 1 01234567 6 jz rel ajmp addr11 xrl direct,a xrl direct,#data xrl a,#data xrl a,direct xrl a,@ri xrl a,rr 0 1 01234567 7 jnz rel acall addr11 orl c,bit jmp @a+dptr mov a,#data mov direct,#data mov @ri,#data mov rr,#data 0 1 01234567 8 sjmp rel ajmp addr11 anl c,bit movc a,@a+pc div ab mov direct,direct mov direct,@ri mov direct,rr 0 1 01234567 9 mov dtpr,#data16 acall addr11 mov bit,c movc a,@a+dptr subb a,#data subb a,direct subb a,@ri sub a,rr 0 1 01234567 a orl c,/bit ajmp addr11 mov bit,c inc dptr mul ab mov @ri,direct mov rr,direct 0 1 01234567 b anl c,/bit acall addr11 cpl bit cpl c cjne a,#data,rel cjne a,direct,rel cjne @ri,#data,rel cjne rr,#data,rel 0 1 01234567 c push direct ajmp addr11 clr bit clr c swap a xch a,direct xch a,@ri xch a,rr 0 1 01234567 d pop direct acall addr11 setb bit setb c da a djnz direct,rel xchd a,@ri djnz rr,rel 0 1 01234567 e movx a,@dtpr ajmp addr11 movx a,@ri clr a mov a,direct (1) mov a,@ri mov a,rr 0 1 0 1 01234567 f movx @dtpr,a acall addr11 movx @ri,a cpl a mov direct,a mov @ri,a mov rr,a 0 1 0 1 01234567
1997 mar 14 60 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 20 limiting values in accordance with the absolute maximum rating system (iec 134) 21 dc characteristics the dc characteristics apply to both the p83cl781 and the p83cl782 unless otherwise stated. v dd = 1.8 to 6 v; v ss =0v; t amb = - 40 to +85 c for the p83cl781 and - 25 to +55 c for the p83cl782; all voltages with respect to v ss unless otherwise speci?ed. see notes 1, 2 and 3. symbol parameter min. max. unit v dd supply voltage - 0.5 +6.5 v v i input voltage on any pin with respect to ground (v ss ) - 0.5 v dd + 0.5 v i i dc current on any input - 5.0 +5.0 ma i o dc current on any output - 5.0 + 5.0 ma p tot total power dissipation - 300 mw t stg storage temperature - 65 +150 c t amb operating ambient temperature - p83cl781 - 40 +85 c operating ambient temperature - p83cl782 - 25 +55 c t j operating junction temperature - +125 c symbol parameter conditions min. typ. max. unit supply v dd supply voltage 1.8 - 6.0 v v dd ram retention voltage in power-down mode 1.0 - 6.0 v i dd supply current operating; p83cl781 v dd =5v; f clk = 12 mhz; note 4 - 17 25 ma v dd =3v; f clk = 3.58 mhz; note 4 - 2.4 5 ma supply current operating; p83cl782 v dd = 3.1 v; f clk = 12 mhz; note 4 - 8.4 12 ma v dd =3v; f clk = 3.58 mhz; note 4 - 2.4 5 m a i dd(idle) supply current idle mode; p83cl781 v dd =5v; f clk = 12 mhz; note 5 - 5.1 12 ma v dd =3v; f clk = 3.58 mhz; note 5 - 0.75 3 ma supply current idle mode; p83cl782 v dd =5v; f clk = 12 mhz; note 5 - 2.7 5 ma v dd =3v; f clk = 3.58 mhz; note 5 - 0.75 3 ma i dd(pd) supply current power-down mode v dd = 1.8 v; t amb =25 c; note 6 -- 10 m a
1997 mar 14 61 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 notes 1. capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the low level output voltage of ale, port 1 and port 3 pins when these make a high-to-low transition during bus operations. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make high-to-low transitions during bus operations. in the most adverse conditions (capacitive loading > 100 pf), the noise pulse on the ale line may exceed 0.8 v. in such events it may be required to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 2. capacitive loading on ports 0 and 2 may cause the high level output voltage on ale and psen to momentarily fall below the 0.9% of v dd specification when the address bits are stabilizing. 3. circuits with power-on reset option off are tested at v ddmin = 1.8 v; with the on option (typically 1.3 v) they are tested at v ddmin = 2.3 v. 4. the operating supply current is measured with all output pins disconnected; xtal1 driven with t r =t f =10 ns; v il =v ss ; v ih =v dd ; xtal2 not connected; ea = rst = port 0 = v dd . 5. the idle mode supply current is measured with all output pins disconnected; xtal1 driven with t r =t f =10ns; v il =v ss ; v ih =v dd ; xtal2 not connected; ea=port0=v dd . 6. the power-down current is measured with all output pins disconnected; xtal1 not connected; ea = port 0 = v dd ; rst=v ss . 7. the input threshold voltage of p1.6/scl and p1.7/sda meet the i 2 c-bus specification. therefore, an input voltage below 0.3v dd will be recognized as a logic 0 and an input voltage above 0.7v dd will be recognized as a logic 1. inputs v il low level input voltage note 7 v ss - 0.3v dd v v ih high level input voltage note 7 0.7v dd - v dd v i il low level input current v dd =5v; v in = 0.4 v; note 7 --- 100 m a v dd = 2.5 v; v in = 0.4 v; note 7 --- 50 m a i il(t) low level input current (high-to-low transition) v dd =5v; v in = 0.5v dd ; note 7 --- 1.0 ma v dd = 2.5 v; v in = 0.5v dd ; note 7 --- 500 m a i li input leakage current v ss < v i < v dd ; note 7 -- 10 m a outputs i ol low level output current; except sda and scl v dd =5v; v ol = 0.4 v 1.6 -- ma v dd = 2.5 v; v ol = 0.4 v 0.7 -- ma i ol1 low level output current; sda and scl v dd =5v; v ol = 0.4 v 3.0 -- ma i oh high level output current (push-pull options only) v dd =5v; v oh =v dd - 0.4 v - 1.6 -- ma v dd = 2.5 v; v oh =v dd - 0.4 v - 0.7 -- ma r rst rst pull-down resistor 10 - 200 k w symbol parameter conditions min. typ. max. unit
1997 mar 14 62 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.33 frequency operating range - p83cl781. 14 4 0 8 mla588 - 1 6 4 2 0 v dd (v) f xtal (mhz) 10 2 6 12 fig.34 frequency operating range - p83cl782. 14 4 0 8 mgc441 6 4 2 0 v dd (v) f xtal (mhz) 10 2 6 12 fig.35 p83cl781: typical operating current as a function of frequency and v dd . 0246 24 18 6 0 12 msa759 - 1 v (v) dd i dd (ma) 8 mhz 3.58 mhz 12 mhz t amb =25 c. oscillator option = oscillator 3. fig.36 p83cl781: typical idle current as a function of frequency and v dd . handbook, halfpage 0246 8 6 2 0 4 msa758 v (v) dd i dd(idle) (ma) 12 mhz 8 mhz 3.58 mhz t amb =25 c. oscillator option = oscillator 3.
1997 mar 14 63 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.37 p83cl782: typical operating current as a function of frequency and v dd . 0246 24 18 6 0 12 mlb166 v (v) dd i dd (ma) 12 mhz 8 mhz 3.58 mhz t amb =25 c. oscillator option = oscillator 3. fig.38 p83cl782: typical idle current as a function of frequency and v dd . 0246 8 6 2 0 4 mlb165 v (v) dd i dd(idle) (ma) 3.58 mhz 8 mhz 12 mhz t amb =25 c. oscillator option = oscillator 3. fig.39 typical power-down current as a function of v dd . handbook, halfpage 0 6 4 2 0 246 msa756 v (v) dd ( a) m i dd(pd) t amb =25 c.
1997 mar 14 64 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 22 ac characteristics the following ac characteristics apply to both the p83cl781 and p83cl782 unless otherwise stated. 22.1 program memory v dd = 5 v; v ss = 0 v; t amb = - 40 to +85 c for the p83cl781 and - 25 to +55 c for the p83cl782; c l = 50 pf for port 0, ale and psen; c l = 80 pf for all other outputs unless specified. see fig.40. symbol parameter f osc = 12 mhz f osc = variable unit min. max. min. max. t ll ale pulse duration 127 - 2t ck - 40 - ns t al address set-up time to ale 43 - t ck - 40 - ns t la address hold time after ale 48 - t ck - 35 - ns t liv time from ale to valid instruction input - 233 - 4t ck - 100 ns t lc time from ale to control pulse psen 58 - t ck - 25 - ns t cc control pulse duration psen 215 - 3t ck - 35 - ns t civ time from psen to valid instruction input - 125 - 3t ck - 125 ns t ci input instruction hold time after psen 0 - 0 - ns t cif input instruction ?oat delay after psen - 63 - t ck - 20 ns t ac address valid after psen 75 - t ck - 8 - ns t aiv address to valid instruction input - 302 - 5t ck - 115 ns t afc address ?oat delay after psen 12 - 0 - ns fig.40 read from program memory. handbook, full pagewidth mla583 t ll ale port 0 port 2 t cy liv t t lc t cc t la t al aiv t afc t civ t t ci t cif address a8 to a15 address a8 to a15 instruction input ad0 to ad7 ad0 to ad7 psen instruction input
1997 mar 14 65 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 22.2 external data memory v dd = 5 v; v ss = 0 v; t amb = - 40 to +85 c for p83cl781 and - 25 to +55 c for the p83cl782; c l = 50 pf for port 0, ale and psen; c l = 40 pf for all other outputs unless specified. see note 1 and figs 41 and 42. note 1. interfacing the p83cl781 or the p83cl782 to devices with float times up to 75 ns is permitted. this limited bus contention will not cause damage to port 0 drivers. symbol parameter f osc = 12 mhz f osc = variable unit min. max. min. max. t rr rd pulse duration 400 - 6t ck - 100 - ns t ww wr pulse duration 400 - 6t ck - 100 - ns t la address hold time after ale 48 - t ck - 35 - ns t rd rd to valid data input - 150 - 5t ck - 165 ns t dfr data ?oat delay after rd - 97 - 2t ck - 70 ns t ld time from ale to valid data input - 517 - 8t ck - 150 ns t ad address to valid data input - 585 - 9t ck - 165 ns t lw time from ale to rd or wr 200 300 3t ck - 50 3t ck +50 ns t aw time from address to rd or wr 203 - 4 - ns t whlh time from rd or wr high to ale high 43 123 t ck - 40 t ck +40 ns t dwx data valid to wr transition 23 - t ck - 60 - ns t dw data set-up time before wr 433 - 7t ck - 150 - ns t wd data hold time after wr 33 - t ck - 50 - ns t afr address ?oat delay after rd - 12 - 12 ns
1997 mar 14 66 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.41 read from data memory. handbook, full pagewidth mla584 ale port 0 port 2 t ld t la t al ad t afr t address a8 to a15 or port 2 output data input ad0 to ad7 psen t whlh aw t t lw t rr t dfr t rd rd fig.42 write to data memory. handbook, full pagewidth mla585 - 1 ale port 0 port 2 t la t al address a8 to a15 or port 2 output data output ad0 to ad7 psen t whlh aw t t lw t ww t wd t dw t dwx wr
1997 mar 14 67 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.43 instruction cycle timing. 1/1 page = 296 mm (datasheet) 27 mm mla929 p1 p2 s1 p1 p2 s2 p1 p2 s3 p1 p2 s4 p1 p2 s5 p1 p2 s6 p1 p2 s1 p1 p2 s2 p1 p2 s3 p1 p2 s4 p1 p2 s5 p1 p2 s6 one machine cycle one machine cycle xtal1 input address a0 - a7 inst. in address a0 - a7 inst. in address a0 - a7 inst. in address a0 - a7 inst. in address a8 - a15 address a8 - a15 address a8 - a15 address a8 - a15 address a0 - a7 inst. in address a0 - a7 inst. in address a0 - a7 data output or data input address a8 - a15 address a8 - a15 or port 2 output address a8 - a15 old data new data sampling time of i/o port pins during input serial port clock port 0, 2, 3 input port 0, 2, 3 output port 2 bus (port 0) read or write of external data memory port 2 bus (port 0) external program memory fetch wr rd only active during a write to external data memory only active during a read from external data memory psen ale dotted lines are valid when rd or wr are active old data new data port 1 output
1997 mar 14 68 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 fig.44 ac testing input waveform. handbook, halfpage mla586 0.9 v 0.4 v 0.7 v 0.3 v 0.7 v 0.3 v test points dd dd dd dd dd dd fig.45 input current. handbook, 4 columns msa763 0.5 v dd v dd 0 100 m a i il(t) i il i i 500 m a
1997 mar 14 69 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 23 package outlines unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot129-1 92-11-17 95-01-14 a min. a max. b z max. w m e e 1 1.70 1.14 0.53 0.38 0.36 0.23 52.50 51.50 14.1 13.7 3.60 3.05 0.254 2.54 15.24 15.80 15.24 17.42 15.90 2.25 4.7 0.51 4.0 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 0.56 0.54 0.14 0.12 0.01 0.10 0.60 0.62 0.60 0.69 0.63 0.089 0.19 0.020 0.16 051g08 mo-015aj m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 40 1 21 20 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) (1) dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
1997 mar 14 70 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.3 2.1 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 19.2 18.2 1.2 0.9 2.4 1.8 7 0 o o 0.15 2.35 0.1 0.3 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 2.0 1.2 sot205-1 92-11-17 95-02-04 d (1) (1) (1) 14.1 13.9 h d 19.2 18.2 e z 2.4 1.8 d b p e q e a 1 a l p q detail x l (a ) 3 b 11 y c d h b p e h a 2 v m b d z d a z e e v m a x 1 44 34 33 23 22 12 133e01a pin 1 index w m w m 0 5 10 mm scale qfp44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm sot205-1 a max. 2.60
1997 mar 14 71 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 0.85 0.75 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 92-11-17 95-02-04 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p q detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1997 mar 14 72 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 24 soldering 24.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 24.2 dip 24.2.1 s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 24.2.2 r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 24.3 qfp 24.3.1 r eflow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9398 510 63011). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary from 50 to 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheat for 45 minutes at 45 c. 24.3.2 w ave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 24.3.3 r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 mar 14 73 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 25 definitions 26 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 27 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 mar 14 74 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 notes
1997 mar 14 75 philips semiconductors product speci?cation low voltage 8-bit microcontrollers with uart and i 2 c-bus p83cl781; p83cl782 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca53 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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